1. Field of the Invention
The present invention relates to a circuit arrangement for digital multiplication of integers, having an encoding unit, which, in particular, can form the logarithm of the to-be-multiplied numbers, an adding unit, which adds the output values of the encoding unit, and a decoding unit, which delogarithmizes the output value of the adding unit.
Microelectronically integrated signal processors have great economic significance for all product sectors. Continued miniaturization has already led to considerable success in digital signal processing practice, e.g. the real time processing of language and image signals.
In this context reference is made, by way of illustration, to the article "Multiplier Policies for Digital Signal Processing" in IEE ASSP Magazine, 1990, pp. 6-20.
Miniaturization and attainable functionality of each microchip have, moreover, resulted in numerous attempts at realization of so-called neuronal networks and computers.
2. Description of the Related Art
Despite the tremendous progress made in miniaturization, the enormous number of convolution operations (multiplications, divisions, additions and substractions), needed, e.g., for the processing of HDTV signals, for real time identification of moving scenes and for the realization of neuronal networks or the like sets limits on raising the calculation speed as well as on further reduction of the "chip areas".
Analog and digital multiplications either have little companding (resolution), respectively are inaccurate (small signal-to-noise ratio) or have to be carried out with long word lengths, respectively be carried out with floating-decimal-point representation making necessary massive parallel processing practically impossible.
Due to accuracy and companding problems in digital processing, complicatedly constructed analog-digital and digital-analog converters with long word lengths are needed for processing the input and output analog signals, e.g., supplied by image sensors, display actuators or the like, which also greatly limit the feasability of such signal processing systems.
For this reason, the older German patent application P 40 33 507.0 describes a circuit arrangement based on the fundamental consideration that in many instances the attempt is made to optimally support and imitate sophisticated, natural processes, such, as e.g. seeing and hearing, with electronic signal processing.
These processes are distinguished by great companding ranges being scanned by so-called adaption for the signals related to seeing and hearing, such as brightness and sound intensity. It has been understood that electronically processable signal deviations, which nonetheless can describe relatively large companding ranges, are obtained by manipulating logarithms of these signals (the so-called logarithmic compressions). This is utilized, e.g., in the pulse code modulation of language and in image sensors using a logarithmic output signal.
Although various companding encodings have hitherto become known, e.g., the encodings according to the .mu.-respectively A principle utilized in language encoding. These encodings were, however, introduced for the special demands of language transmission and are hardly generally applicable.
The known circuit arrangements for digital multiplication of integers, using an encoding unit, which forms the logarithms of the to-be-multiplied numbers, an adding unit, which adds the output values of the encoding unit, and a decoding unit, which delogarithmizes the output value of the adding unit, have however the drawback that both the "logarithmizing" and the "delogarithmizing" are time consuming and require a relatively large chip area corresponding to the suitable circuit elements.